NAND Flash Programmer - High Speed / High Density Device Programmer - Flash Memory Resources
Advantages of NAND
Because of the efficient architecture of NAND flash, its cell size is much smaller than a NOR cell. This, in combination with a simpler production process, enables NAND architecture to offer higher densities with more capacity on a given die size. The cost per bit is much lower than NOR. As a result, more bits of NAND memory have been sold than any other type.
NAND is not, however, a perfect memory. As a result of the extremely small scaling and the NAND architecture, it is susceptible to data retention issues and to bits becoming unusable. Because of these imperfections in NAND, complex software needs to be used to administer things like wear-leveling, error correction, and bad block management. It also complicates the file systems used with NAND devices.
Data I/O and NAND
Data I/O has been supporting NAND devices since the beginnings of its FlashCORE programmer line around 2001. As a result, we have years of expertise in dealing with NAND devices, including supporting hundreds of bad block schemes and Error Correction Codes. We have worked with many different embedded file systems and operating systems, including nearly all of the major mobile operating systems.
There are different types of NAND devices. Many NAND devices fall in the category of "bare" NAND or "raw" NAND. These devices have all of the issues with wear-leveling, error correction, and bad block schemes.
Another type of NAND devices is "managed" NAND, sometimes referred to as embedded flash drives. These devices are NAND stacked with a controller that manages the wear-leveling, error correction codes, and bad blocking schemes. An example of this type of device would be embedded MMC.
Increasing NAND Densities
Because of the increasing need to get higher density devices and lower cost per bit, NAND flash vendors are trying many different strategies. The most common strategies is to use increasingly smaller lithography width and to increase from one bit per cell to multiple bits per cell. As the lithography gets smaller and as the number of bits per cell increases to 2, 3, or 4 bits, the memory density increases correspondingly. However, there are tradeoffs associated with this move related to read/write speeds, data retention, endurance, and error correction complexity. Dealing with these tradeoffs requires increasingly complicated controllers and software methods.
Rely on Data I/O for all your NAND programming needs
Whether using multi-bit per cell NAND or a complex managed NAND with the latest interface, Data I/O is the leading expert on programming. Contact us today to discuss NAND or submit a device support request for your NAND requirements.